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aug. 2000 ver 0.4 data sheet S1D2503X01-D0B0 preliminary
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 1 preliminary i 2 c bus controlled r/g/b video amplifier the S1D2503X01-D0B0 is a very high frequency video amplifier system with i 2 c bus control used in monitors with high resolution up to 1600 1200. it contains 3 matched r/g/b video amplifiers with osd interface and provides flexible interfacing to i 2 c bus controlled adjustment systems. functions ? i 2 c bus controlled 200mhz rgb video pre-amplifier for monitors ? the S1D2503X01-D0B0 is a very high frequency video amplifier system with osd interface controlled by i 2 c bus. ? all controls and adjustments are digitally performed thanks to i 2 c bus. : contrast, brightness and dc output level of r/g/b signals common to the 3-channel and drive adjustment (sub contrast), cut-off control (ac or dc coupling by ct bit) is separated for each channel. ? the S1D2503X01-D0B0 is included video & osd half tone function. ? the white blance adjustment is effective on brightness, video & osd signals. ? the S1D2503X01-D0B0 works for application using ac or dc coupled crt driver. ? in addition to beam current limitation (abl), osd intensity interface and brightness uniformity (bu) interface are possible with external pins. ordering information features ? 3-channel matched r/g/b video amplifier ? i 2 c bus control items - contrast control - brightness control - sub contrast control for each channel - osd contrast control - cut-off control for each channel - brightness control for cut-off - switch registers for sblk, half tone, cut-off int/ext, bps (blank pulse input polarity selection) and cps (clamp pulse input polarity selection). ? built in clamp gate with anti osd sagging ? built in osd interface, osd blk ? built in osd intensity interface ? built in abl (automatic beam limitation) device package operating temperature S1D2503X01-D0B0 32-dip-600a -25 c ? +80 c 32-dip-600a ? built in video input clamp, brt clamp ? built in video & osd half tone function on osd picture (osd raster 8 colors and 3 raster selection by hr/g/b) ? built in smooth video contrast control with external capacitor. ? 3-channel r/g/b video amplifier 200mhz @f-3db ? ttl osd inputs, 80mhz bandwidth ? contrast control range: 38db ? sub contrast control range: 11db ? osd contrast control range: 38db ? capable of 7vp-p output swing ? high speed osd blk
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 2 preliminary block diagram figure 1. block diagram interface & control half-tone 1 2 3 9 5 6 7 8 18 32 4 22 10 23 11 15 vi/ osd_sw osd interface clp video osd switch osd raster osd contrast video contrast video half- tone + sub contrast rosd gosd bosd vdd rin vcc1 gnd1 gin int b/u clp bin blk vss c1 gm1 + gm2 30 31 21 27 26 25 24 19 28 29 20 12 14 13 + + blk clp osd intensity b/u interface clamp gate video/osd switch blank gate video half-tone osd raster select clp blk i 2 c bus control cut off cut off bright (06h) rout rclp rct vcc gnd bout bclp bct gout gclp abl sda scl gct cut off ext offset d3:4 (0bh) cut off int/ext switch d2 (0bh) r/g/b cut off control (07/08/09h) brightness control (01h) r/g/b drive control (02/03/04h) osd cont control (05h) contrast contral (00h) 17 dtest video-half tone switch d0 (0ah) osd raster color d1: 6 (0ah) d4: 6 (0ch) soft blank d0 (0bh) blank polarity select d1 (0bh) clamp polarity select d5 (0bh) one (red) of three channels
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 3 preliminary pin configuration figure 2. pin configuration S1D2503X01-D0B0 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 32 31 30 29 28 27 26 25 23 24 22 21 20 19 18 16 17 rosd gosd bosd vi/ osd_sw rin vcc1 gnd1 gin bin vdd vss abl scl sda c1 b/u rclp rout gclp gout vcc2 gnd2 bout blk bclp clp rct gct bct int dtest
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 4 preliminary table 1. pin configuration (continued) pin no symbol i/o configuration 1 rosd i red osd input 2 gosd i green osd input 3 bosd i blue osd input 4 vi/osd_sw i video or osd switch 5 rin i red video input 6 v cc1 - v cc (normal) 7 gnd1 - ground1 (normal) 8 gin i green video input 9 v dd - v dd (logic) 10 bin i blue video input 11 vss - ground (logic) 12 abl i automatic beam limit 13 scl i/o serial clock 14 sda i/o serial data 15 c1 - contrast cap 16 - - - 17 dtest - - 18 int - osd intensity 19 bct i blue cut off control 20 gct i green cut off control 21 rct i red cut off control 22 clp i clamp gate signal input 23 blk i blank gate signal input 24 bclp - blue clamp cap 25 bout o blue video output 26 gnd2 - ground2 (drive part) 27 v cc2 - v cc (drive part) 28 gout o green video output 29 gclp - green clamp cap 30 rout o red video output 31 rclp - red clamp cap 32 b/u i brightness uniformity
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 5 preliminary pin description table 2. pin description pin no pin name schematic description 1 2 3 red osd input (rosd) green osd input (gosd) blue osd input (bosd) osd input signals are in ttl level and will be connected to ground when switching to video input 4 video/osd switch (vi/osd_sw) video/osd signal is switched by pin4 dc level pin4 = ?high?, osd input pin4 = ?low?, video input 5 8 10 red video input (rin) green video input (gin) blue video input (bin) max input video signal is 0.7vpp 6 v cc1 - normal power supply (12v) 7 gnd1 - normal ground 9 vdd - logic power supply (5v) 11 vss - logic ground 0.2k vcc osdin 5k 100k 0.2k vcc osdsw 5k 100k pin4 output high osd low video 1.5k vcc 1.9v 1.5k clp 0/150ua 0.2k 15k video_in 0.2k
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 6 preliminary 12 abl auto beam limitation input (control range: 0.5 ? 4.5v) 13 14 serial clock input (scl) serial data input (sda) scl, sda for i 2 c bus control 15 contrast cap1 - external contrast cap pin 17 dac test pin dac current (0 - 500ua) table 2. pin description (continued) pin no pin name schematic description 1k vcc 25k 1k 10k 2k 2k 100k vdd scl sda 2v vcc 1k 1k
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 7 preliminary 18 osd intensity input (int) active high 19 20 21 blue cut-off control (bct) green cut-off control (gct) red cut-off control (rct) cut-off control output 22 clamp gate input (clp) video amp active when clamp gate signal is in low ttl level. clamp gate min. pulse width : 0.2us, at fh: 50khz 23 blank gate input (blk) video amp blanks video signal when blank gate signal is in low ttl level. table 2. pin description (continued) pin no pin name schematic description 0.2k vcc int 5k 100k ctx 100ua 100ua cs1 cs2 0.2k 0-500ua cut-off 0-200ua cut-off brt 0.2k vcc clp 5k cps bit clp signal 0 low 1 high 0.2k vcc blk 5k bps bit blk signal 0 low 1 high
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 8 preliminary 31 29 24 red clamp cap (rclp) green clamp cap (gclp) blue clamp cap (bclp) brightness control activated by charging and discharging of the external cap. (0.1 m f) (during clamp gate) 30 28 25 red video output (rout) green video output (gout) blue video output (bout) video signal output 26 gnd2 - drive ground 27 vcc2 - drive power supply (12v) 32 brightness uniformity (bu) bu interface input table 2. pin description (continued) pin no pin name schematic description 0.22k ext.cap 0.22k iclamp 0.04k vcc 0.02k 0.04k 1k vcc 4.8v 1k 1k bu 1k
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 9 preliminary absolute maximum rating (ta = 25 c) (see 1) thermal & esd parameter table 3. absolute maximum rating no item symbol value unit min typ max 1 maximum supply voltage v cc 1/2 - - 13.2 v 2 operating temperature (see 2) topr -25 - 80 c 3 storage temperature tstg -65 - 150 c 4 operating supply voltage vccop 11.4 12.0 12.6 v (see 3) 5 power dissipation p d - - 1.38 w 6 logic part power supply v dd - - 5.5 v table 4. thermal & esd parameter no item symbol value unit min typ max 1 thermal resistance (junction-ambient) q ja - 50 - c/w 2 junction temperature tj - 149 - c 3 human body mode (c = 100p, r = 1.5k) hbm 2 - - kv 4 machine model (c = 200p, r = 0) mm 300 - - v 5 charge device model cdm 800 - - v
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 10 preliminary electrical characteristics dc electrical characteristics ta = 25 c, v cc1 = v cc2 = 12v; v dd = 5v; pin1, 2, 3, 4 = 0v; pin22 4v; pin18, 32 = 0v; por; unless otherwise stated table 5. dc electrical characteristics parameter symbol conditions min typ max unit supply current i cc (see 4) 80 110 140 ma maximum supply current iccmax v cc1, 2 = 15v 100 140 180 ma video input bias voltage vbias 1.6 1.9 2.2 v clamp gate low input voltage v22l p 22 = 4v ? 0v 1.0 1.5 2.0 v clamp gate high input voltage v22h p 22 = 0v ? 4v 1.0 1.5 2.0 v clamp gate low input current i22l -8 -4 - ua clamp gate high input current i22h p 22 = 12v - 3 6 ua clamp cap charge current iclamp+ p 24, 29, 31 = 4v 0.4 0.8 1.2 m a clamp cap discharge current iclamp- p 24, 29, 31 = 8v -1.2 -0.8 -0.4 m a blank gate low input voltage v23l p 23 = 4v ? 0v 1.0 1.5 2.0 v blank gate high input voltage v23h p 23 = 0v ? 4v 1.0 1.5 2.0 v blank gate low input current i23l p 23 = 0v -8 -4 - ua blank gate high input current i23h p 23 = 12v - 3 6 ua brt output voltage (por) vopor p 22 = s8 (pulse width 0.2us/38khz) 0.9 1.4 1.9 ua black level voltage channel difference d vo bl (see 5) -0.3 - 0.3 v clamp cap high voltage v_clp v cc1, 2 = 15v 8 10 12 v video output high voltage voh p 22 = 4v 6.2 7.5 9 v video blank output voltage vob - 0.1 0.2 v scl high input current i13h - 0.01 1 ua sda high input current i14h - 0.01 1 ua scl/sda low level input voltage vbusl ob: o/h, scl/sdt signal high = 3.5v, low = 1.5v - - 1.5 v scl/sda high level input voltage vbush 3.5 - - v scl/sda input pin ref. voltage vbusr p 13, 14 = open status 1.5 2.0 2.5 v video input resistance videoin 10 100 - k w spot killer voltage vspot v cc1, 2 = 12 ? 9v 9.2 10.4 11.2 v por ext. cut-off output current ictxpo 150 250 350 ua cut-off min. output voltage difference d vcutmin d vcutmin = vout [07, 08, 09: 00h] - vout [por] -0.6 -0.4 -0.2 v cut-off max. output voltage difference d vcutmax d vcutmax = vout [07, 08, 09: ffh] - vout [por] 0.2 0.4 0.6 v
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 11 preliminary ext. cut-off output current range d ictx ob: 04h, p 19, 20, 21 = 5v, d ictx = p20?s i [07, 08, 09: ffh] - p20?s i [07, 08, 09: 00h] 330 480 630 ua cut-off brt output current range d ictbrt ob: 04h, p 19, 20, 21 = 5v, d ictbrt = p20?s i [06:ffh] - p20?s i [06:00h] 130 200 330 ua ext. cut-off offset output current1 ics1 ob: 04h, p 19, 20, 21 = 5v, 06 - 09: 00h, cs1 bit = 1 60 90 120 ua ext. cut-off offset output current2 ics2 ob: 04h, p 19, 20, 21 = 5v, 06 - 09: 00h, cs2 bit = 1 60 90 120 ua video soft blank output voltage vosoft ob: 01h - 0.1 0.2 v wrong slave address det. wsaddr ob: 01h, when wrong slave address is inputted you must measure voltage. 0.9 1.4 1.9 v blank polarity selector voltage vbps ob: 02h - 0.1 0.2 v clamp polarity selector voltage vcps ob: 20h 0.9 1.4 1.9 v video brightness low output voltage vobl 01: 00h - 0.1 0.2 v video output worst low output vlow -0.2 - 0.2 v video brightness high output voltage vobh 01: ffh 2.2 2.8 3.4 v bu input bias voltage vbu 01: 80h 4 4.8 5.6 v table 5. dc electrical characteristics (continued) parameter symbol conditions min typ max unit
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 12 preliminary ac electrical characteristics ta = 25 c, v cc1 = v cc2 = 12v; v dd = 5v; pin1, 2, 3, 4 = 0v; pin5, 8, 10 = s1; pin23 = 4v; pin22 = s8; pin18, 32 = 0v; por. vin = 0.56vpp manually adjust video output pins 25, 28 and 30 to 4v dc for the ac test (see 11) unless otherwise stated (see 12) table 6. ac electrical characteristics parameter symbol conditions min typ max unit video bandwidth (see 7,8) f -3db p 5, 8, 10 = s2, 00, 02, 03, 04 = ffh when p 22 = 0v, you must measure clamp cap pin voltage. then p 22 = 4v, p 8 = 2.2v, clamp cap pin = above measurement voltage. 200 250 - mhz video amp gain avmax p 22 = s8 (low: 0.5v, high: 3v) 00, 02, 03, 04 = ffh 15.5 17.5 19.5 db max. gain channel difference d avmax (see 6,7) avmax = 20log (vout / vin) d avmax =20log (voutch1 / vontch2) -1 - 1 db low gain channel difference d avlow (see 6,7) p 22 = s8 (low: 0.5v, high: 3v), 00 = 40h, 02, 03, 04 = ffh d avlow = 20log (voutch1 / voutch2) -1 - 1 db sub drive ctrl max-center avdmax avdmax = 20log (vout [02, 03, 04: 80h]/ vout [02, 03, 04: ffh]) -5 -4 -3 db sub drive ctrl min-center avdmin avdmin = 20log (vout [02, 03, 04: 00h]/ vout [02, 03, 04: 80h]) -11 -8 -5 db contrast ctrl max-center avcmax avcmax = 20log (vout [02, 03, 04: 80h]/ vout [02, 03, 04: ffh]) -7.5 -6 -4.5 db contrast ctrl min-center avcmin avcmin = 20log (vout [00:00h] / vout [00, 02, 03, 04: 80h]) - - -35 db abl control range d abl 00, 02, 03, 04 = ffh, d abl = 20log (vlow [p12 = 0.5v] / vmax [p12 = 5v]) -14.5 -11.5 -8.5 db bu modulation ratio1 bu1 p 32 = s9 6 12 18 % bu modulation ratio2 bu2 18 24 30 % video amp thd thd p 5, 8, 10 = s5, p22 = 4v, p 24, 29, 31 = var. - 1 5 % video rising time (see 7) tr p 5, 8, 10 = s6, p 24, 29, 31 = var. - 1.4 1.8 ns video falling time (see 7) tf - 1.4 1.8 ns blank output rising time (see 7) trblank p 22 = 0v, p 23 = s7 - 3 10 ns blank output falling time (see 7) tfblank - 5 12 ns blank rising prop. delay trblankpr - 25 35 ns blank falling prop. delay tfblankpr - 15 25 ns video output channel crosstalk 10khz ct_10k (see 9) p 5 = s3, p 22 = 4v, 00, 02, 03, 04: ffh - -65 -45 db video output channel crosstalk 10mhz ct_10m (see 7,9) when p 22 = 0v, you must measure clamp cap pin voltage. then p 22 = 4v, video input pin = 2.2v dc bias, clamp cap pin = above measurement voltage ct-10k = 20log (voutch2 / voutch2 [avmax vout]) - -50 -35 db
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 13 preliminary osd electrical characteristics ta = 25 c, v cc1 = v cc2 = 12v; v dd = 5v; pin1, 2, 3, 4 = 4v; pin23 = 4v; pin12, 18, 22, 32 = 0v; por; unless otherwise stated table 7. osd electrical characteristics parameter symbol conditions min typ max unit osd low input voltage v osd l p 4 = s7, p 1, 2, 3 = 4v ? 0v 2.0 2.5 3.0 v osd high input voltage v osd h p 4 = s7, p 1, 2, 3 = 0v ? 4v 2.0 2.5 3.0 v osd select low input voltage vosdsl p 4 = s7 (s7?s level 5vpp ? 0vpp) 2.0 2.5 3.0 v osd select high input voltage vosdsh p 4 = s7 (s7?s level 0vpp ? 5vpp) 2.0 2.5 3.0 v osd output voltage vosd p 1, 2, 3 = 3v, p 4 = s7, 05: ffh 2.6 3.6 4.6 v pp osd gain channel difference d vosd p 1, 2, 3 = 3v, p 4 = s7, 05: ff, d vosd = vosdch1 - vosdch2 -300 - 300 mvpp osd attenuation vosdatt p 1, 2, 3 = 3v, p 4 + s7, vosdatt = vosd [05:80h] / vosd [05:ffh] 100 30 50 70 % osd low gain channel difference d vosdl p 1, 2, 3 = 3v, p 4 + s7, d vosdl = vosdch1 [05:80h] - vosdch2 [05:80h] -300 - 300 mvpp video/osd switch time tr (osd-s) p 4 = s7, p 22 = s8 - 4 10 ns osd/video switch time tf (osd-s) - 4 10 ns video/osd prop. delay tr-prop (osd-s) - 5 15 ns osd/video prop. delay tf-prop (osd-s) - 10 20 ns osd rising time trosd p 1, 2, 3 = s7, p 4, 22 = s8 - 4 8 ns osd falling time tfosd - 4 8 ns osd rising prop. delay tr-prop - 5 15 ns osd falling prop. delay tf-prop - 5 15 ns video/osd 10mhz crosstalk ctvi/osd-10m p 1, 2, 3 = none, p 5, 8, 10 = s4, p 22 = s8, 00, 02, 03, 04, 05: ffh) ctvs/osd-10m = 20log (vout [p 4 = s8] / vout [p 4 = 0v]) - -50 -35 db r osd ht attenuation (blue) vhtbluer p 1, 2, 3 = 4v, p 4 = s7, p 22 = s8, 05: ffh vhtblue = vout [04:41h] / vout [04:00h] 100 80 100 120 % g osd ht attenuation (blue) vhtblueg 80 100 120 % b osd ht attenuation (blue) vhtblueb 30 50 70 % r osd ht attenuation (white) vhtwhiter p 1, 2, 3 = 4v, p 4 = s7, p 22 = s8, 05: ffh vhtwhite = vout [04:48h] / vout [04:00h] 100 30 50 70 % g osd ht attenuation (white) vhtwhiteg 30 50 70 % b osd ht attenuation (white) vhtwhiteb 30 50 70 % osd intensity attenuation vintatt p 4 = s7, p 22 = s8, 05: ffh, oa: 00h vintatt = vout [p 18 = 0v] / vout [p 18 = 3v] 100 30 50 70 % osd contrast low output v ocl p 4 = s7, p 22 = s8, 05: 00h, v cc1, 2 : 15v v1 = 4v, p 2, 3 = 0v, p 4 = s7, p 22 = s8, 00, 02, 03, 04, 05: ffh - - 0.2 vpp osd output channel crosstalk v osdct -0.3 - 0.3 vpp
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 14 preliminary i 2 c bus recommended operating conditions i 2 c bus timing requirement table 8. i 2 c bus recommended operating conditions parameter symbol min typ max unit input high level voltage vinh 3.0 - - v input low level voltage vinl - - 1.5 v scl clock frequency f scl - - 200 khz hold time before a new transmission can start t buf 1.3 - - us hold time for start condition t hds 0.6 - - us set-up time for stop conditions t sup 0.6 - - us the low period of scl t low 1.3 - - us the high period of scl t high 0.6 - - us hold time data t hdat 0.3 - - us set-up time data t supdat 0.25 - - us rise time of scl t r - - 1.0 us fall time of scl t f - - 3.0 us figure 3. i 2 c bus timing requirement t buf sda scl t hds t supdat t high t sup t hdat t low
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 15 preliminary notes: 1. absolute maximum rating indicates the limit beyond which damage to the device may occur. 2. operating ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. for guaranteed specifications and test conditions, see the electrical characteristics. the guaranteed specifications appl y only for the test conditions listed. some performance characteristics may degrade when the device is not operated under the listed test conditions. 3. v cc supply pins 6, and 27 must be externally wired together to prevent internal damage during v cc power on/off cycles. 4. the supply current specified is the quiescent current for v cc 1 /v cc 2 and v dd with rl = , the supply current for v cc2 (pin 27) also depends on the output load. 5. output voltage is dependent on load resistor. test circuit uses rl = 390 w 6. measure gain difference between any two amplifiers vin = 560mvpp. 7. when measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed circuit board without socket is recommended. video amplifier 10mhz isolation test also requires this printed circuit board. the reason for a double sided full ground plane pcb is that large measurement variations occur in single sided pcbs. 8. adjust input frequency from 10mhz (av max reference level) to the-3db frequency (f -3db). 9. measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. terminate the undriven amplifier inputs to simulate generator loading. repeat test at fin = 10mhz for iso_10mhz. 10. a minimum pulse width of 200 ns is guaranteed for a horizontal line of 15khz. this limit is guaranteed by design. if a lower line rate is used a longer clamp pulse may be required. 11. during the ac test the 4v dc level is the center voltage of the ac output signal. for example. if the output is 4vpp the signal will swing between 2v dc and 6v dc. 12. these parameters are not tested on each product which is controlled by an internal qualification procedure.
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 16 preliminary test signal format table 1. test signal format signal name input signal formal signal description s1 video gain measurement video = 1mhz/0.056vpp (half-tone: 5mhz) sync = 50khz s2 video bandwidth measurement video = 1 - 200mhz/ 0.56vpp s3 cresstalk (10khz) measurement video = 10khz/0.56vpp s4 cresstalk (10mhz) measurement video = 10mhz/0.56vpp s5 thd measurement video = 19khz/0.56vpp sync [v] 4us [t] video [v] video 2v [t] [v] video 2v [t] [v] video 2v [t] video [t] 0.56vpp [v]
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 17 preliminary table 1. input signal formal (continued) ? s1, s6, s7, s9 signal?s low level must be synchronized with the s8 signal?s sync. term. ? the input signal level uses the ic pin as reference signal name input signal formal signal description s6 video tr/tf measurement video = 200khz/0.7vpp (duty = 50%) s7 osd gain, osd tr/tf, propagation delay measurement osd s/w input osd = 200khz/5vpp (duty = 50%) s8 clamp gate input clamp = 50khz (5vpp) (half-tone: 200khz) tsync = 0.2us s9 bu input (200khz) - bu1 = 1.25vpp - bu2 = 2.5vpp video [t] 0.56vpp [v] osd [t] 5vpp duty = 50% [v] clamp [t] tsync = 0.2us [v] [t] 1.25/ 2.5vpp [v]
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 18 preliminary functional description osd intensity input (active: high) this input pin is used to indicate the osd color intensity. thus, 16 color selection is achievable by combining this intensity pin with r/g/b osd input. osd inputs the S1D2503X01-D0B0 includes all the circuitry necessary to mix osd signals into the r/g/b video signal. you need 4 pins for function. (r/g/b osd, osd blanking) data transfer all bytes are sent msb (most significant bit) bit first and the write data transfer is closed by a stop. the mcu can write data into the S1D2503X01-D0B0 registers. to do that, after a start, the mcu must send: ? the i 2 c address slave byte with a low level for r/w bit (bit1) ? the byte of the internal register address where the mcu wants to write data (sub address) ? the data ? stop serial interface the 2-wires serial interface is an i 2 c bus interface. the slave address of the S1D2503X01-D0B0 is dc (hexadecimal) i 2 c bus write operation: a complete data transfer bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 1 1 0 1 1 1 0 0 (w) stop ack data byte ack ack register address slave address start generated by slave w msb lsb scl sda transfer
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 19 preliminary data transfer format ? 1byte data transfer ? multi data transfer ? automatic increment the automatic increment feature of the sub address enables a quick slave receiver initialization within one transmission, by the i 2 c bus controller sta slave adrs w a sub adrs a data a sto sta slave adrs w a sub adrs a data a sub adrs a data a data a sub adrs a data a sto sta slave adrs w a auto adrs (1xxx0000) a data (sub: 00h) a data (sub: 01h) a data (sub: 03h) a data (sub: 09h) a data (sub: 0ah) a data (sub: 0bh) a sto
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 20 preliminary sub address allocation map (slave address: dch) ? sblk: soft blanking switch (1: on, 0: off) ? cps: clamping input polarity selection (1: pos., 0: neg.) ? bps: blanking input polarity selection (1: pos., 0: neg.) ? ht: video & osd half tone (1: on, 0: off) ? hr/hg/hb: osd raster color switch for video half tone (ht = 1) ? ct: cut-off control int/ext (0: int/1: ext) ? cs1/2: extended cut-off brightness control data bits (cs1 = 100ua/cs2 = 100ua) sub address (hex) function dac bits int. value (hex) d7 d6 d5 d4 d3 d2 d1 d0 00h contrast control 8 bits 80h 01h brightness control (3-ch) 8 bits 80h 02h sub contrast control (r) 8 bits 80h 03h sub contrast control (g) 8 bits 80h 04h sub contrast control (b) 8 bits 80h 05h osd contrast control 8 bits 80h 06h cut-off brightness control 8 bits 80h 07h cut-off control (r) 8 bits 80h 08h cut-off control (g) 8 bits 80h 09h cut-off control (b) 8 bits 80h 0ah - hb2 hg2 hr2 hb1 hg1 hr1 ht - 00h 0bh - - cps cs2 cs1 ct bps sblk - 00h 0ch - hb3 hg3 hr3 t4 t3 t2 t1 - 0fh osd raster1 osd raster2 osd raster3 half tone hr1 hg1 hb1 hr2 hg2 hb2 hr3 hg3 hb3 0 0 0 0 0 0 0 0 0 black (initial) 0 0 1 0 0 1 0 0 1 blue 0 1 0 0 1 0 0 1 0 green 0 1 1 0 1 1 0 1 1 cyan 1 0 0 1 0 0 1 0 0 red 1 0 1 1 0 1 1 0 1 magenta 1 1 0 1 1 0 1 1 0 yellow 1 1 1 1 1 1 1 1 1 white
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 21 preliminary register description contrast (osd contrast adjustment) (8-bits) the contrast adjustment is made by controlling simultaneously the gain of three internal variable gain amplifiers through the i 2 c bus interface. the contrast adjustment allows you to cover a typical range of 38db. brightness adjustment (8-bits) the brightness adjustment controls to add the same black level (pedestal) to the 3-channel/r/g/b signals after contrast amplifier by i 2 c bus. cut-off brightness adjustments (8-bits) the cut-off brightness adjustment is made by simultaneously controlling the external cut-off current. sub contrast adjustment (8-bits 3) the sub contrast adjustment allows to cover a typical range of 12db. cut-off adjustments (8-bits 3) these adjustments are used to adjust the white balance, and the gain of each channel is controlled by i 2 c bus. contrast register (sub adrs: 00h) (vin = 0.56vpp, bright: 40h, sub: ffh) brightness register (3-ch) (sub adrs: 01h) (cont: 40h, sub: ffh) sub contrast register (3-ch) (sub a]drs: 02/03/04h) (vin = 0.56vpp, bright: 40h, cont: ffh) hex bits contrast (vpp) gain (db) int. value (hex) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 0 0 0 0 0 0 0 -30.0 80 1 0 0 0 0 0 0 0 1.12 11.5 o ff 1 1 1 1 1 1 1 1 4.2 17.5 increment/bit 0.0164 hex bits brightness (v) int. value (hex) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 0 0 0 0 0 0 0 80 1 0 0 0 0 0 0 0 1.4 o ff 1 1 1 1 1 1 1 1 2.8 increment/bit 0.0109 hex bits sub contrast (vpp) gain (db) int. value (hex) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 0 0 0 0 0 0 1.33 7.5 80 1 0 0 0 0 0 0 0 2.65 13.5 o ff 1 1 1 1 1 1 1 1 4.2 17.5 increment/bit 0.0123
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 22 preliminary osd contrast register (sub adrs: 05h) (vosd = ttl, bright: 40h, sub: ffh) cut-off brightness register (3-ch) (sub adrs: 06h) cut-off register (3-ch) (sub adrs: 07/08/09h) (cont = 80h, subcont: ffh) ? int: ct = 0 ? ext: ct = 1 hex bits osd contrast (vpp) gain (db) int. value (hex) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 0 0 0 0 0 0 0 - 80 1 0 0 0 0 0 0 0 2.0 - o ff 1 1 1 1 1 1 1 1 4.0 - increment/bit 0.0156 hex bits cut-off brightness (ua) int. value (hex) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 0 0 0 0 0 0 0 80 1 0 0 0 0 0 0 0 100 o ff 1 1 1 1 1 1 1 1 200 increment/bit 0.781 hex bits cut-off int (v) int. value (hex) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 0 0 0 0 0 0 -0.4 80 1 0 0 0 0 0 0 0 0 o ff 1 1 1 1 1 1 1 1 0.4 increment/bit 0.0031 hex bits cut-off ext (ua) int. value (hex) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 0 0 0 0 0 0 0 80 1 0 0 0 0 0 0 0 250 o ff 1 1 1 1 1 1 1 1 480 increment/bit 1.875
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 23 preliminary recommendation 12v power routing because S1D2503X01-D0B0 is a wideband amp of above 200mhz, 12v power significantly affects the video characteristics. the effects from the inductance and capacitance are different for each board, and , therefore, some tuning is required to obtain the optimum performance. the output power, vcc2, must be separated from vcc1 using a bead or a coil, which is parallel-connected to the damping resistor. in the case of using a coil , the appropriate coil value is between 20uh - 200uh. parallel-connected a variable resistor to the coil and control its resistance to obtain the optimum video waveform. (bead use: refer to application circuit ) (moreover, bead can be replaced using a coil and variable resistor to obtain the optimum video waveform.) vcc1 12v power use a 104 capacitor and large capacitor for the power filter capacitor. 12v output stage power vcc2 do not use the power filter capacitor or use a capacitor smaller than 22pf, because it is an important factor of video oscillation. output stage gnd2 care must be taken during routing because it ,as an amp output stage gnd, is an important factor of video oscillation. r/g/b clamp cap and r/g/b load resistor must be placed as close as possible to the gnd2 pin. gnd2 must be arranged so that it has the minimum gnd loop. r/g/b clamp capacitor use the 104 capacitor for normal r/g/b clamps. during the clamp signal's input period, the clamp stage compares the video output's pedestal level and the level adjusted by sub address 01. if an error is detected, current is charged/discharged to the clamp capacitor, so that the video output pedestal level is set to the adjusted level. the current charged/discharged to the clamp cap is about 750ua. the capacitor value is very important. if the r/g/b clamp cap's charge current is different for each channel, the screen can first appear to be red or blue, then later become normal when you turn the power on. in that case, it is best to change the clamp cap value to adjust the charge/discharge time. dc coupling capacitor select the video input dc coupling cap with sagging in mind. select from between 10uf and 0.1uf. brightness uniformity(modulation means suppressing the ratio to the video output level) the brightness uniformity feature using the pre amp directly influences the video signal, so it can influence the focus as well. therefore, it is best to minimize the modulation degree as much as possible. try not to go above10%. when not using the ic's b/u feature, connect it to a capacitor of about 0.1uf and short it to gnd.
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 24 preliminary
i 2 c bus controlled r/g/b video amplifier for monitors S1D2503X01-D0B0 25 preliminary application board circuit s1d2503x01- d0b0 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 32 31 30 29 28 27 26 25 23 24 22 21 20 19 18 16 17 rosd gosd bosd vi/osd_sw rin vcc1 gnd1 gin bin vdd vss abl scl sda c1 b/u rclp rout gclp gout vcc2 gnd2 bout blk bclp clp rct gct bct int dtest rosd in gosd in bosd in vi/osd sw in red in 10u + + 0.075k 0.033k 10u 0.1u green in 10u + + 0.075k 0.033k 10u 0.1u + blue in 0.075k 4.7u abl in scl sda 0.1k 0.1k + 4.7u vdd = 5v 2k 2k int in 0.033k 0.033k 0.033k 0.033k 0.033k 0.033k 0.1k 0.1k 0.1k 0.1k 1u 75k 1u 12v 75v 75k 75k b drive out cathode b 1u 75k 1u 12v 75v 75k 75k cathode g g drive out 1u 75k 1u 12v 75v 75k 75k r drive out cathode r clp in 0.1k blk in 0.39k + 0.1u 10u vdd = 5v bout gout 0.1u 0.1u 0.1u rout bu in + 10u + 0.1u 470u vcc = 12v bav21 bav21 bav21 10u 0.39k 0.39k bead bead ksp42 ksp92 ksp42 ksp92 ksp42 ksp92
S1D2503X01-D0B0 i 2 c bus controlled r/g/b video amplifier for monitors 26 preliminary typical application circuit kb2503 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 32 31 30 29 28 27 26 25 23 24 22 21 20 19 18 16 17 rosd gosd bosd vi/osd_sw rin vcc1 gnd1 gin bin vdd vss abl scl sda c1 b/u rclp rout gclp gout vcc2 gnd2 bout blk bclp clp rct gct bct int dtest rosd in gosd in bosd in vi/osd sw in red in 10u + + 0.075k 0.033k 10u 0.1u green in 10u + + 0.075k 0.033k 10u 0.1u + blue in 0.075k 0.1u abl in scl sda 0.1k 0.1k + 4.7u vdd = 5v 2k 2k int in 0.033k 0.033k 0.033k 0.033k 0.033k 0.033k 0.1k 0.1k 0.1k 0.1k 1u 75k 1u 12v 75v 75k 75k cathode b 1u 75k 1u 12v 75v 75k 75k cathode g 1u 75k 1u 12v 75v 75k 75k cathode r clp in 0.1k blk in 0.39k + 0.1u 10u vdd = 5v 0.1u 0.1u 0.1u bu in + 10u + 0.1u 10u vcc = 12v bav21 bav21 bav21 10u 0.39k 0.39k bead bead ksp42 ksp92 ksp42 ksp92 ksp42 ksp92 rin gin vcc rout gout bin bout 10 10 10 27 27 27 0.1uf 0.1uf 0.1uf 100uf 0.1uf 75v + vee 0.1uf + 100uf vcc = 12v s1d2503x01- d0b0 470u 4.7u 4 . 7 u

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